1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of programming the same. More particularly, the invention relates to a semiconductor memory device comprising a plurality of memory cells, each including a selection transistor and a plurality of phase change variable resistors and a method of programming same.
A claim of priority is made to Korean Patent Application No. 10-2004-0085801 filed on Oct. 26, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A Phase-Change Random Access Memory (PRAM) is a device that stores data using a phase change material such as a chalcogenide alloy that changes into one phase under some heating and cooling conditions, and changes into another phase under different heating and cooling conditions. Typically, the two phases respectively comprise a crystalline phase and an amorphous phase. A PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
A PRAM has a low resistance value when in the crystalline phase and a high resistance value when in the amorphous phase. Accordingly, a logic state for the PRAM is determined to be either “0” or “1” depending on its resistance value. Generally, the crystalline phase of the PRAM corresponds to a programmed state, i.e., a logical “0”, and the amorphous phase corresponds to a reset state, i.e., a logical “1”.
The PRAM is changed into an amorphous phase by heating it to a temperature greater than a melting temperature of the phase change material and then rapidly cooling it down. The PRAM is changed into the crystalline phase by heating it to a temperature lower than the melting temperature of the phase change material for a predetermined length of time.
The phase change material used to form the PRAM plays an important role in the PRAM's functionality. The phase change material is typically composed of chalcogenide, which is an alloy composed of germanium (Ge), antimony (Sb), and tellurium (Te), or in other words, a GST alloy. Where the GST alloy is heated or cooled, its state changes between the amorphous state (reset state) and the crystalline state (set state). By using the amorphous state and the crystalline state to represent different logic states, i.e., a logical “1” and a logical “0”, the GST alloy can be used to form a memory device.
A memory cell formed of chalcogenide typically includes an upper electrode, a chalcogenide layer, a lower electrode contact, a lower electrode, and an access transistor. Data is read from the memory cell by measuring a resistance value of the chalcogenide layer. The memory cell is programmed by changing the chalcogenide layer between the amorphous, or reset state, and the crystalline, or set state.
To write a logical “1” to the memory cell, the chalcogenide layer is heated to a temperature greater than or equal to its melting temperature and then rapidly cooled down, thereby changing the chalcogenide layer to the amorphous state. To write a logical “0” to the memory cell, the chalcogenide layer is maintained at a temperature below its melting temperature, and then cooled down, thereby causing the chalcogenide layer to assume the crystalline state.
FIG. 1 is a circuit diagram of a conventional phase change memory cell 10 disclosed in U.S. Pat. No. 5,883,827. Memory cell 10 includes a phase change variable resistor “R” having one end connected to a bit line BL and another end connected to a drain of a selection transistor N10. Selection transistor N10 has a gate connected to a word line WL and a source connected to a reference voltage (not shown).
FIG. 2 is a circuit diagram of a non-volatile phase change memory cell 30 disclosed in U.S. Patent Publication No. 2004/0114428. Memory cell 30 includes a plurality of variable resistors, each having one end connected to a corresponding bit line BL and another end connected to a drain of a selection transistor N30. Selection transistor N30 has a gate connected to a word line WL and a source connected to a reference voltage (not shown) via a source line SL.
U.S. Patent Publication No. 2004/0114428 teaches that memory cell 30 may be a resistance control nonvolatile random access memory, a magnetic RAM, or an Ovonic Unified Memory (OUM). However, it does not teach a circuit construction on which a programming or read operation for the phase change memory cell may be performed, nor does it teach a method of programming the phase change memory cell.
Accordingly, there is a need for a circuit construction adapted for reading and programming a PRAM and methods of programming the PRAM. In addition, in order for the PRAM, which has attracted attention as a next-generation memory, to compete with existing memory devices such as DRAM, SRAM, and flash memory, the PRAM needs to become more highly integrated, so as to become smaller and faster.